The present invention relates to a non-volatile semiconductor memory device and a method for manufacturing the same and, particularly, an improvement in or relating to the manufacturing step of forming the laminated gate structure thereof.
An EEPROM is a kind of non-volatile semiconductor memory device in which data can be electrically rewritten or reloadable and, known as such a memory device is an MOS transistor which comprises a laminated gate structure consisting of a charge storage layer (floating gate) and a control gate.
FIG. 1A is a plan view showing the memory cells of an FETMOS type EEPROM which is one type of EEPROM, and FIG. 1B is a sectional view taken along the line 1B--1B in FIG. 1A.
As shown FIGS. 1A and 1B, on a p-type silicon substrate (or a p-type well) 100, there is formed a thermally oxidized oxide or thermal oxide film (SiO.sub.2) constituting element isolation regions. The element isolation regions 101 define element regions 102 in the surface of the substrate 100. In the portion of the substrate 100 which lies under the element isolation regions 101, p+ type channel stoppers 103 are formed. In the element regions 102, n+ type source and drain regions 110 are formed. The portion of the respective element region 102 which lies between the source and drain regions 110 constitutes a channel region 104. Formed on the channel region 104 is a thin oxide film (SiO.sub.2) 105 through which a tunnel current can be made to flow. The oxide film 105 is a gate insulation film. On the oxide film 105, a floating gate 106, an inter-layer insulation film 107 and a control gate 108 are successively formed. The inter-layer insulation film 107 insulates the floating gate 106 and the control gate from each other and, at the same time, capacitively couple said control gate 108 and said floating gate 105 to each other. Due to this, the inter-layer insulation film 107 is formed of, e.g. silicon dioxide or a so-called ONO (oxide-nitride-oxide) film formed by successively laminating silicon dioxide, silicon nitride and silicon dioxide one upon another. Further, the laminated gate structure consisting of the floating gate 106, the inter-layer insulation film 107 and the control gate 108 is formed in a continuous patterning manner using a photo resist mask (not shown) patterned into a control gate pattern. Due to this, the edges of the floating gate 106 and the edges of the control gate 108 are matched with each other. The source and drain regions 110 are formed by injecting an n-type impurity into the substrate 100 by means of ion implantation, using as a mask the laminated gate structure and the element isolation regions 101, respectively.
In the case of the memory cells shown in FIGS. 1A and 1B, used for the element isolation regions 101 is a thermally oxidized oxide film or thermal oxide film formed by the use of the LOCOS (Local Oxidation Of Silicon) method. FIGS. 2A and 2B show typical manufacturing process according to the LOCOS method.
As shown in FIG. 2A, according to the LOCOS method, a nitride film (Si.sub.3 N.sub.4) 200 is formed in the surface portions of the substrate 100 other than the surface portions of the substrate 100 in which the element isolation regions are formed. After this, as shown in FIG. 2B, the surface of the substrate 100 is thermally oxidized to a considerable thickness. Since the nitride film 200 functions as a barrier film against oxidation, the thermal oxide film (SiO.sub.2) is formed on the (surface) portions of the surface of the substrate 100 which are not covered by the nitride film 200. The thermal oxide film thus formed constitutes the element isolation regions 101. Further, in FIG. 2A, the reference numeral 300 denotes a buffer oxide film.
In the case of the LOCOS method, as is well known, wedge-shaped oxide films known as "bird's beaks" in the respective interface between the nitride film 200 and the substrate 100. The bird's beaks result in causing a conversion error between the designed structure and the actually completed structure. Due to this, each element isolation region 101, that is, the actual width dimension S.sub.A of the element isolation region 101 becomes larger by, e.g. an amount corresponding to the conversion error than the designed width dimension S.sub.D. According to the LOCOS method which has such a defect, it is very difficult to form each element isolation region 101 the smallest width of which is 0.5 .mu.m or less.
Further, in the case of employing the LOCOS method, the portion of the thermal oxide film which is formed in the interior of the substrate 100 is only about half of the whole thickness thereof. Due to this, the element isolating ability exhibited in the interior of the substrate 100 is scanty, and it is also difficult to narrow the interval for element isolation.
Further, the remaining portion of the thermal oxide film comes out to the surface of the substrate 100, so that, in the surface of the substrate, "differences in level" are caused. The "differences in level" thus caused in the surface of the substrate 100 results in lowering the processing margin in the lithography step, so that even the formation of fine patterns are made difficult.
As an element isolation technique for overcoming such a difficulty, the trench element isolation technique has come to be developed according to which trenches are formed in the substrate, and the interiors of the trenches are filled up with an insulation material.
FIG. 3A is a plan view of the memory cell of an FETMOS type EEPROM formed by the use of the trench element isolation technique, and FIG. 3B is a sectional view taken along the line 3B--3B in FIG. 3A. In FIGS. 3A and 3B, the portions corresponding to those shown in FIGS. 1A and 1B are referenced by the same reference numerals for omission of the description thereof and for giving a description of only different portions.
As shown in FIGS. 3A and 3B, in a substrate 100, trenches 111 for element isolation are formed. The interiors of the trenches 111 are filled with an element isolating insulation material such as, e.g. silicon dioxide, whereby trench type element isolation regions 112 are formed.
In the trench type element isolation regions 112, no bird's beak is produced; and thus, no conversion error exists between the designed structure and the actually completed structure.
Further, in the case of the respective trench type element isolation region 112, the portion thereof which is formed in the interior of the substrate 100 can be determined depending on the depth of the trench 111, so that element isolation regions formed deeply in the interior of the substrate can be realized. As a result, the element isolation ability can be enhanced; and the interval required for isolation of the elements from each other can be more reduced than in the case of the element isolation regions formed in accordance with the LOCOS method. Due to this, the interval for element isolation can be decreased to a substantial degree. In this way, by introducing the trench element isolation technique, the miniaturization of the element isolation regions becomes possible.
However, in the case of the memory cells of an EEPROM, there is another structural portion which is an obstacle to the miniaturization. That is "wings" 113 of each floating gate 106. The "wings" 113 are formed in a state extended onto the element isolation regions. Due to the fact that the floating gates 106 have the "wings" 113, the mutually opposed areas of each floating gate 106 and the associated control gate 108 spread, so that the capacitance between the floating gate 106 and the control gate 108 increases. However, the design-wise minimum dimension is restricted by the distance between the "wings" 113, that is, the dimension of a "slit" 114 for separating the floating gates 106 from each other, so that the merit due to the trench element isolation technique is belittled.
Further, the respective floating gate 106 must be formed on the channel region 104 without fail. For instance, if the mask shifts out of position, so that the edge of the particular floating gate 106 comes to be disposed on the channel region 104, then, when the laminated gate structure is formed by etching, even the element region 102 be etched. Due to such circumstances, it must be ensured that the amount of mismatch or positional shift of the mask in the lithographic step must be made smaller than the width of the "wing" 113.
For instance, in case the trench type element isolation region 112 is formed with a width of 0.4 .mu.m, and the "slit" 114 is formed with a width of 0.2 .mu.m, the width of the "wing" 113 becomes 0.1 .mu.m. In this case, the amount of positional shift or mismatch of the mask in the lithographic step must be held down to 0.1 .mu.m or less. Accordingly, in the case of the memory cells shown in FIGS. 3A and 3B, it is considered that a further miniaturization thereof is very difficult.
The technique according to which the miniaturization of the element isolation regions and the miniaturization of the memory cells can be achieved at the same time was reported by Aridome et al. in the IEDM in 1994; that is, the so-called "self-aligning trench element isolation technique".
FIG. 4A is a plan view of the memory cells of an FETMOS type EEPROM formed by the use of the self-aligning trench element isolation technique, and FIG. 4B is a sectional view taken along the line 4B--4B in FIG. 4A. In FIGS. 4A and 4B, the portions corresponding to those shown in FIGS. 1A and 1B are referenced by the same reference numerals for omission of the description thereof, and only the different portions will be described.
As shown in FIGS. 4A and 4B, trench type element isolation regions 112 is formed in a state self-aligning with the side walls of the floating gates 106. Due to this, the floating gates 106 have no "wing". Due to the fact that the floating gates 106 have no "wing", the memory cells can be more miniaturized than the memory cells shown in FIGS. 3A and 3B.
In the case of the FETMOS type EEPROM, as shown in FIG. 4B, a voltage VCG applied to the control gate 108 is divided by the capacitance C1 constituted through the gate oxide film 105 between the floating gate 106 and the channel 104 and the capacitance C2 constituted through the inter-layer insulation film 107 between the floating gate 106 and the control gate 108. The voltage VFG effectively applied to the capacitance C1 is represented as follows: EQU VFG={C2/(C1+C2)}.multidot.VCG.
In the case of the FETMOS type EEPROM, the capacitance C2 is increased in order to reduce the voltage VCG applied to the control gate at the time of writing or erasure through the FN tunneling (Fowler-Nordheim tunneling). Here, the "wings" turn out to be an important element. In the memory cells shown in FIGS. 4A and 4B, no "wing" exists, but a portion of the side wall of each floating gate 106 is exposed from the element isolation region 112, so that, in this exposed portion, the floating gate 106 and the control gate 108 are opposed to each other to increase the capacitance C2.
FIGS. 5 to 13 are, respectively, perspective views showing the manufacturing steps for the manufacture of an FETMOS type EEPROM by the use of the self-aligning trench element isolation technique. In FIGS. 5 to 13, the pattern of an NOR type EEPROM is shown by way of example.
First, as shown in FIG. 5, a gate oxide film 105 is formed in the surface of a p-type silicon substrate (or a p-type well) 100. Next, on the thus formed gate oxide film 105, silicon is deposited to form a polycrystalline silicon film 106 which is used as a floating gate later. Further, on this polycrystalline silicon film 106, silicon nitride (Si.sub.3 N.sub.4) is deposited to form a silicon nitride film 201 which is used as a mask later. Subsequently, the portions of the silicon nitride film 201 which lie on the regions which will be used as the trench type element isolation regions later are etched. Then, by the use of the silicon nitride film 201 as a mask, the polycrystalline silicon film 106 and the gate oxide film 105 are anisotropically etched. Subsequently, the substrate 100 is anisotropically etched to form trenches 111. Then, after the side walls of the trenches 111 are subjected to a washing treatment, a thin insulation film such as, e.g. a thin thermal oxide film (SiO.sub.2) (not shown) is formed on said side walls. Further, in order to enhance the threshold voltage and the punch-through voltage of the parasitic MOSFET constituted in the portion of the substrate 100 which lies beneath each trench 111, boron is injected by ion implantation into the substrate 100 from the bottom of the respective trench 111, whereby a channel stopper 103 is formed. The channel stoppers 103 may be formed as required. The depth of the trenches 111 can be suitably selected by taking into consideration the threshold voltage of the parasitic MOSFET formed in the portion of the substrate 100 lying beneath each trench 111 and the punch-through voltage.
Next, as shown in FIG. 6, an insulating material such as TEOS or BPSG is deposited, whereby the trenches 111 and the openings formed in the laminated structure consisting of the gate oxide film 105, the polycrystalline silicon film 106, and the nitride film 201 are filled up with burying or burying members 112. Then, by the use of the chemical-mechanical polishing (CMP) method or the etch-back method, the surfaces of the burying or filling members 112 thus deposited are flattened.
Subsequently, as shown in FIG. 7, the surface portions of the polycrystalline silicon film 106 are exposed, and the surfaces of the buried members 112 and the surface portions of the polycrystalline silicon film 106 are further flattened so that said surfaces may positionally coincide with one another. Then, the buried members 112 are further dry-etched or wet-etched, whereby the side walls of the polycrystalline silicon film 106 are exposed. The height of the thus exposed side walls is determined depending on the area necessary to obtain a desired capacitance C2 as described above. Subsequently, the thus exposed side walls of the polycrystalline silicon film 106 are washed.
Next, as shown in FIG. 8, on the buried members 112 and the polycrystalline silicon film 106, a silicon oxide film (SiO.sub.2), a silicon nitride film (Si.sub.2 N.sub.4) and a silicon oxide film (SiO.sub.2) are successively laminated, thus forming a laminated ONO film 107 which will be used later as an inter-layer insulation film for insulating the floating gate and the control gate from each other. Then, on the laminated ONO film 107, polycrystalline silicon is deposited to form an electrically conductive polycrystalline silicon film 108 which will be used later as a control gate is formed. In this case, the surface of the polycrystalline silicon film 108 has differences in level in the portions lying on the respective buried members 112 since the surfaces of the buried members 112 recede from the surface of the polycrystalline silicon film 106.
Subsequently, as shown in FIG. 9, on the polycrystalline silicon film 108, a photo resist is applied, forming a photo resist layer 202. Then, the photo resist layer 202 is patterned into control gate patterns by the use of the lithography method. Next, by the use of the photo resist layers 202 as a mask, the portion of the polycrystalline silicon film 108 other than the portions thereof which will be rendered into the control gates is completely removed by anisotropic etching until the ONO film 107 comes to be exposed; and thus, said first-mentioned portion is wholly removed.
Next, as shown in FIG. 10, the ONO film 107 is anisotropically etched, in which case the buried members 112 lying under the ONO film 107 are also etched, so that the surfaces of the buried members 112 partially recede, thus causing a "film decrease or loss". In FIG. 10, the original surfaces of the buried members 112 are shown by a broken line.
Next, as shown in FIG. 11, the polycrystalline silicon film 106 is anisotropically etched. As a result, the polycrystalline silicon film 106 is separated from memory to memory, thus assuming its shape as the floating gate 106. At the same time, the ONO film 107 assumes its shape as the inter-layer insulation film 107 which insulates the floating gate 106 and the control gate 108 from each other, and the polycrystalline silicon film 108 assumes its shape as the control gate 108 of the memory cell. In this way, the laminated gate structures 203 each consisting of the control gate 108, the inter-layer insulation film 107 and the floating gate 106 are completed. Further, the buried members 112 assume their shape as the trench type element isolation regions 112.
Next, as shown in FIG. 12, after or before the photo resist layer 202 is removed, a donor impurity such as phosphorus is injected into the substrate 100 by ion implantation to form source regions 110S and drain regions 110D by the use of the laminated gate structures 203 and the element isolation regions 112.
Next, as shown in FIG. 13, there is formed an inter-layer insulation film 204 which is buried in to fill up the portions between the laminated gate structures 203 to insulate said laminated gate structures 203 from each other; in the inter-layer insulation film 204, contact holes 205 leading to the drain regions 110D are formed; and, on each inter-layer insulation film 104, there are formed bit lines 206 which are electrically connected to the drain regions 110D through the contact holes 205, with which the memory cells of the EEPROM are completed.
However, in the case of the above-mentioned processing method and memory cell structure, as is apparent particularly from FIG. 10, the surfaces of the buried members 112 are partially exposed, and thus, there is the fear that they may be exposed to the etching treatment etc. and thus shaven off in the ensuing steps. Due to this, there is the further fear that the fine "voids" produced when the trenches 111 are filled up with the buried members 112 may spread to deteriorate the element isolation ability; and further, on the surfaces of the completed trench type element isolation regions 112, "differences in level" are produced, as a result of which there is caused the fear that, when the inter-layer insulation film 204 is buried in, an "insufficient burying-in" may be caused due to said "differences in level".
Further, as shown in FIG. 11, in case the surfaces of the buried members 112 largely recede, the element regions (the semiconductor substrate 100) are exposed, so that, when the polycrystalline silicon film 106 is being etched, the substrate 100 may be etched at the same time.
The "film decrease or loss" of the surfaces of the element isolation regions results in the deterioration in electrical characteristics of the memory cell array of the EEPROM due to the "insufficient burying-in" etc. as mentioned above or causes an unnecessary etching of the element regions in some cases. This in turn brings about inconvenient circumstances such as, e.g the fall in yield of EEPROMs.
Further, the "film decrease or loss" of the surfaces of the element isolation regions is a phenomenon which takes place not only in the case of the above-mentioned self-aligning trench isolation technique but also in the case of any product having laminated gate type memory cells such as an EEPROM which has a LOCOS type element isolation regions as shown in FIGS. 1A and 1B or an EEPROM which has a trench type element isolation regions as shown in FIGS. 3A and 3B.